Single-walled carbon nanotubes (SWNTs) have many superior properties suitable for beyond CMOS (complementary metal oxide semiconductor) technology scaling and high-sensitivity chemical and biological sensors. However, the high growth temperatures for SWNTs have inhibited the integration of SWNTs onto a CMOS platform. Although some low-temperature growth methods have recently been reported, compatibility with foundry CMOS processes still remains a challenge. As an example, adding photomasks to the CMOS fabricating process causes technical difficulty and high cost. In addition, interfacing to discrete SWNT devices can be difficult and cumbersome.
Chemical vapor deposition (CVD) appears to be the most promising technique currently available to synthesize single-walled carbon nanotubes (SWNTs) for several reasons: (1) CVD produces pristine, defect-free, and high-quality nanotubes without any by-products such as amorphous carbon; (2) CVD requires no post-growth processing, such as purification, sonication, or filtering; (3) CVD is a well-established technique in the semiconductor industry, such that the existing expertise can easily be transferred and adapted to nanotube growth; and (4) CVD is scalable to larger substrates and wafer sizes.
Despite these advantages, however, a major problem with CVD growth is that it requires high temperatures (typically 800-1000° C.), making it difficult, if not impossible, to integrate CVD SWNTs onto a CMOS platform. As an alternative, plasma enhanced CVD (PECVD) has been used to grow SWNTs at temperatures as low as 600° C. [Li et al., “Preferential growth of semiconducting single-walled carbon nanotubes by a plasma enhanced CVD method,” Nano Letters 4, 317 (2004)]; however, even this temperature is too high for post-CMOS processing. Also, forming an interface to SWNT devices is often cumbersome.
Recently, room-temperature SWNT growth has been realized using localized resistive heating on thermally isolated microelectromechanical systems (MEMS) structures [Englander et al., “Local synthesis of silicon nanowires and carbon nanotubes on microbridges,” Applied Physics Letters 82, 4797 (2003)], but this growth method has been limited to non-CMOS substrates because the employed micromachining processes are not compatible with post-CMOS processing. Nanotube growth may be applied before or in between CMOS process steps (i.e., pre-CMOS or intra-CMOS), but would cause serious contamination problems and temperature constraints. Moreover, the requirement of the additional masks for nanotube growth, MEMS fabrication, and thermal isolation would make the fabrication very expensive, especially for prototyping, even in the post-CMOS case.
Accordingly, a fabrication technique that can deposit SWNTs on CMOS substrate and achieve SWNTs-to-CMOS interconnect without the need of any post-CMOS photomasks is desirable.